1. Field of the Invention
This invention relates generally to an analog-digital converter which uses a dual-slope method, and more particularly, to an analog-digital converter in which two known reference voltages whose polarities are the same as that of the unknown input voltage to be converted are used as the input voltages to the integrator.
2. Description of the Prior Art
An analog-digital converter which uses a dual-slope method is known. This kind of converter basically comprises an integrator, a comparator, switching circuits and a switch control circuit. The integrator further includes a D.C. amplifier, an input resistor and a feed-back capacitor as shown in FIG. 1.
In this kind of converter, a known analog reference voltage having a polarity opposite to that of the analog input voltage to be converted is used as one of the input voltages to the integrator.
In FIG. 1, the analog input voltage to be converted V.sub.s is supplied to an input terminal 1a and analog reference voltage -V.sub.r whose polarity is opposite to that of the input voltage V.sub.s is supplied to an input terminal 1b.
At first, the input terminal 1a is connected to a terminal 3 in the switch circuit 2 according to the output signal from a switching control circuit 9. As a result thereof, the input voltage V.sub.s is integrated by the integrator 4 consisting of the D.C. amplifier 5, the input resistor 6 and the feed-back capacitor 7.
The comparator 8 compares the level of the integrated voltage V.sub.o with the level of a fixed reference voltage V.sub.c . After the input voltage V.sub.s is supplied to the amplifier 5 for the period T.sub.1 , the switching control circuit 9 generates a signal to the switching circuit 2 and the input terminal 1b is connected to the terminal 3. As a result thereof, the reference voltage -V.sub.r is integrated by the integrator 4.
FIG. 2 shows an integrated voltage V.sub.o . In FIG. 2, T.sub.2 is the period in which the reference voltage -V.sub.r is supplied to the integrator 4. T.sub.1 is a predetermined period and T.sub.2 is a period measured in the switch control circuit 9.
In this case, if the D.C. amplifier 5 has not offset, the following relative equation is applicable ##EQU1##
T.sub.1 and T.sub.2 are measured by counting the clock pulses in the switching control circuit 9. Consequently, the ratio V.sub.s /V.sub.r can be obtained as the ratio T.sub.2 /T.sub.1 and the digital quantity of the analog voltage V.sub.s may be obtained.
However, the D.C. amplifier 5 generally has an offset. Therefore, the above relative equation is not applicable. Instead, the following relative equation is applicable ##EQU2## where .DELTA. V is the offset voltage of the D.C. amplifier 5.
Consequently, the ratio V.sub.s /V.sub.r cannot be obtained as the ratio T.sub.2 /T.sub.1 .
Therefore, manual adjustment of the D.C. amplifier 5 is necessary to compensate for .DELTA.V. Moreover, it is necessary to carry out a zero-adjustment and a full-scale adjustment everytime prior to actual measurement because the offset voltage .DELTA.V varies as a result of the temperature or as a result of other circumstances.
In order to automatically compensate for the offset voltage .DELTA.V the following method has been suggested. Namely, as shown in FIG. 3, a serial connection circuit of switching circuit 11 and capacitor 12 is provided between the output terminal of the integrator 4 and the ground, and the interconnecting point of the serial circuit is connected to a gate terminal of a field-effect transistor (FET) 13. And further, a source terminal of the FET 13 is connected to a terminal 14 in the switching circuit 2.
In this construction, at first, the terminal 14 is connected to the terminal 3 and the switching circuit 11 is closed. As a result thereof, the current .DELTA.V/R flows through the input resistor 6 and the feed-back capacitor 7 is charged. When the circuit assumes its stationary state, the voltage level of an input terminal 15 of the D.C. amplifier 5 and the level of the source terminal of the FET 13 are equal to each other. Therefore, current does not flow through the input resistor 6. Under this situation, the voltage level of the source terminal of the FET 13 is equal to -.DELTA.V.
Subsequently, the switching circuit 11 is opened and a terminal 16 is connected to the terminal 3 by the output signal from the switching control circuit 9. Therefore, the voltage (V.sub.s -.DELTA.V) is integrated by the integrator 4.
This integration operation is continued for the period T.sub.1 . After that, the terminal 17 is connected to the terminal 3 and then the voltage (-V.sub.r -.DELTA.V) is integrated. This integration operation is continued until the comparator 8 generates the output signal.
In this case, the following relative equation is applicable. EQU (V.sub.s -.DELTA. V+ .DELTA. U) T.sub.1 + (-V.sub.r -.DELTA. V+ .DELTA. V) T.sub.2 = 0
where T.sub.2 is the period in which the voltage (- V.sub.r -.DELTA. V) is integrated.
Therefore, the following relative equation can be obtained. ##EQU3##
This method shows that the opposite polarity voltage -.DELTA.V is previously obtained and, in the actual measuring operation, the combined voltage of V.sub.s and -.DELTA.V or -V.sub.r and -.DELTA.V in integrated.
Consequently, according to this method, the zero-adjustment and full-scale-adjustment are automatically carried out.
In the above-mentioned prior art, however, it is necessary that the polarities of the converted voltage V.sub.s and standard voltage -V.sub.r be opposite each other. Generally, two voltage sources are required in order to obtain two voltages of different polarities. In this case, it is quite difficult to maintain the two voltages at predetermined levels. Further, the abberations of the two voltages have a direct effect upon the digital quantities of the converted voltage even though the D.C. amplifier does not have the offset.
Furthermore, even when two voltages of opposite polarity are obtained from one voltage source, it is quite difficult to maintain the voltages at predetermined levels because of the abberration generated by the polarity converter, which abberration directly affects the accuracy of the A-D conversion.